Design Verification (DV) Engineer

Connected Systems has a client in the Boston, MA area with a perm/direct hire opening for a Design Verification Engineer with 2-10 years of formal design verification experience. Work as part of small DV team where you get the opportunity to learn a lot and make a positive impact on the company’s and your own success.

Although work is in Boston, our client does allow for flex time and work from home option a couple days a week, once you have come up to speed.

Working with experienced DV and Design engineers, you will be design and execute test plans.
Design Test benches
Design verification strategies for ASICs and FPGAs
Perform coverage analysis

BSEE, CE or related technical degree is required
Must have 2+ years of real world (non academic) ASIC or FPGA Design verification experience
Must have experience with SystemVerilog and/or Verilog
Experience with UVM or OVM or related
Good software skills, including C, C++, Python

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